1. Field of the Invention
The present invention relates to a manufacturing method of a thin film transistor having a Gate-Overlapped-LDD (GOLD) structure.
2. Description of the Related Art
To improve reliability, a thin film transistor employs a GOLD structure. This structure is formed as follows. That is, first, low dose amount regions (LDD regions) are formed after a gate electrode is once formed. Thereafter, a gate electrode is formed again, so that source/drain regions are formed. Thus, the LDD regions are formed under the gate electrode by performing a photoengraving process twice for forming a gate electrode, as disclosed in JP-A-2000-91591 and JP-A-2000-349297.
According to the aforementioned method of manufacturing the GOLD structure, the gate electrode is formed by performing the photoengraving process twice. Thus, the aforementioned method has a problem that the number of processes increases. Also, because the gate electrode is formed by performing the photoengraving process twice, it is highly likely that asymmetry occurs between the left and right LDD regions due to the accuracy of overlapping between the first formed gate electrode and the second formed gate electrode. Thus, the aforementioned method has a problem that it is difficult to suppress variation in characteristics.